In flip chip processing of integrated circuit (IC) chips, C4 solder bumps are typically used to connect IC dies to packaging. However, due to the coefficient of thermal expansion (CTE) mismatch between different layers in the packaging, C4 solder bumps can experience large stresses which can lead to crack formation during chip joining. These CTE mismatches must be managed, especially in lead free (Pb-free) solder bumps, to control cracking during chip joining (referred to as “white bump formation”).
One solution for reducing stress translated in the back end of line (BEOL) process involves the use of an organic, buffering layer beneath the interconnect bump, on the chip side between the bump and the BEOL dielectric/copper wiring levels. However, this buffering layer (e.g., a photosensitive polyimide (PSPI) layer) is most effective when its thickness is in the range of 8-12 microns, or even higher. Unfortunately, at those thicknesses, other unintended consequences can occur, such as film formation issues, wafer warpage, and a limited ability to form the requisite small offset final via structure. Therefore, although a thick PSPI layer can be an effective white bump risk reduction measure, the thick (and typically multi-coat) PSPI layer also drives excessive and unacceptable wafer warpage. Also, with aluminum final metal, a blanket PSPI layer underneath can be risky, for example, because the PSPI layer can have entrapped corrosives which may outgas later and attack the Aluminum layer.
While attempts have been made to include a polyimide layer beneath an aluminum pad structure in the form of a redistribution layer (RDL), these attempts have several limitations and associated concerns. This type of RDL structure, typically including patterning an aluminum pad on a blanket film of PSPI and then depositing a second PSPI layer, results in a thick PSPI layer (i.e., the thickness of the two PSPI layers). In addition to the unmanageable level of wafer warpage that results from doing this, the thick PSPI layer in the field area of the chip gives rise to potential reliability issues because standard aluminum plasma gases or strip processes can degrade the polyimide surface, causing corrosive materials to become embedded in the polyimide. These materials can react with the aluminum metallic pad/line sidewall, causing metal corrosion of critical features. Also, the resist used to form the aluminum pattern may become difficult or impossible to remove cleanly, leaving debris on top of the metal pad lines.